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-- Company: 
-- Engineer:
--
-- Create Date:   00:08:10 11/03/2010
-- Design Name:   
-- Module Name:   E:/Dev/VHDL/state_machine/tb_state_machine.vhd
-- Project Name:  state_machine
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: STATE_MACHINE
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY tb_state_machine IS
END tb_state_machine;
 
ARCHITECTURE behavior OF tb_state_machine IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT STATE_MACHINE
    PORT(
         clk : IN  std_logic;
         reset : IN  std_logic;
         launch_scan : IN  std_logic;
         scan_period_elapsed : IN  std_logic;
         end_gw_config : IN  std_logic;
         res_reg_buf_full : IN  std_logic;
         end_of_chain : IN  std_logic;
         shift : OUT  std_logic;
         capture : OUT  std_logic;
         update : OUT  std_logic;
         gwen : OUT  std_logic;
         resetn : OUT  std_logic;
         req_irq : OUT  std_logic;
		 status : OUT std_logic_vector(3 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal reset : std_logic := '0';
   signal launch_scan : std_logic := '0';
   signal scan_period_elapsed : std_logic := '0';
   signal end_gw_config : std_logic := '0';
   signal res_reg_buf_full : std_logic := '0';
   signal end_of_chain : std_logic := '0';

 	--Outputs
   signal shift : std_logic;
   signal capture : std_logic;
   signal update : std_logic;
   signal gwen : std_logic;
   signal resetn : std_logic;
   signal req_irq : std_logic;
   signal status : std_logic_vector(3 downto 0);

   -- Clock period definitions
   constant clk_period : time := 1us;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: STATE_MACHINE PORT MAP (
          clk => clk,
          reset => reset,
          launch_scan => launch_scan,
          scan_period_elapsed => scan_period_elapsed,
          end_gw_config => end_gw_config,
          res_reg_buf_full => res_reg_buf_full,
          end_of_chain => end_of_chain,
          shift => shift,
          capture => capture,
          update => update,
          gwen => gwen,
          resetn => resetn,
          req_irq => req_irq,
		  status => status
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100ms.
      wait for 100ms;	

      wait for clk_period*10;

      -- insert stimulus here 
		launch_scan <= '1';
		scan_period_elapsed <= '1';
		end_gw_config <= '1';
		res_reg_buf_full <= '1';
		end_of_chain <= '1';
      wait;
   end process;

END;
